1. Technical Field
The present invention relates to an electrostatic protection circuit for protecting a semiconductor integrated circuit apparatus from electrostatic discharge (ESD). The invention further relates to a semiconductor integrated circuit apparatus embedded with such an electrostatic protection circuit.
2. Related Art
A semiconductor integrated circuit apparatus may be provided with an electrostatic protection circuit to prevent destruction of an internal circuit caused by static electricity. In general, an electrostatic protection circuit is connected between a first terminal to which a potential of a high-potential side is supplied and a second terminal to which a potential of a low-potential side is supplied. For example, when a positive electric charge is applied to the first terminal due to electrostatic discharge, the positive electric charge is discharged to the second terminal via the electrostatic protection circuit. In this case, an excessive voltage is not applied to the internal circuit, and hence destruction of the internal circuit can be prevented.
As related technology, JP-A-2009-182119 discloses an electrostatic discharge protection circuit aiming to sufficiently discharge an electric charge attributed to electrostatic discharge and to remove noise during a normal operation. This electrostatic discharge protection circuit includes a first power supply line, a second power supply line, a time constant circuit, an inverter, and a second N-channel transistor. When connected to a direct-current power supply, the first power supply line has a first potential and the second power supply line has a second potential that is lower than the first potential. The time constant circuit is composed of a capacitor and a first N-channel transistor that are connected in series between the first power supply line and the second power supply line, the first N-channel transistor having a negative threshold voltage. An input side of the inverter is connected to a connection node between the capacitor and the first N-channel transistor, and an output side thereof is connected to a gate of the first N-channel transistor. The second N-channel transistor is connected between the first power supply line and the second power supply line, and a gate thereof is indirectly connected to the connection node between the capacitor and the first N-channel transistor. The second N-channel transistor becomes electrically conductive in response to an increase in a potential of the gate caused by an increase in a potential of that connection node.
When an ESD event occurs in this electrostatic discharge protection circuit, the potential of the connection node between the capacitor and the first N-channel transistor increases rapidly, and a low-level signal is output from the inverter. This low-level signal is input to the gate of the first N-channel transistor. Therefore, the value of on-resistance of the first N-channel transistor is large, and the first N-channel transistor hence serves as a high resistor that, together with the capacitor, composes a CR time constant circuit. Also, this low-level signal is indirectly input to the gate of the second N-channel transistor. As a result, the second N-channel transistor is placed in an on state, thereby allowing a surge current attributed to the ESD event to escape.
As described above, according to the invention of JP-A-2009-182119, the second N-channel transistor is placed in the on state only for a time period corresponding to the value of a time constant CR determined by a product of the capacitance value of the capacitor and the value of on-resistance of the first N-channel transistor (e.g., a value on the order of several MΩ, due to the input of the low-level signal), and the surge current attributed to the ESD event is discharged during that time period.
JP-A-2009-182119 (paragraphs 0014 to 0016, FIG. 1) is an example of related art.
However, in the electrostatic discharge protection circuit shown in FIG. 1 of JP-A-2009-182119, whether or not to start a protection operation is not determined based on a magnitude of voltage applied to a time constant circuit 11, but is determined based solely on the steepness of a rise in the voltage applied to the time constant circuit 11. Therefore, if the time constant is set so as to achieve sufficient protection characteristics against electrostatic discharge, the protection operation could possibly be started in response to a steep rise in a power supply voltage even during a normal operation.
Also, the on period of an N-channel transistor 14 connected between power supply lines is determined based on a time constant of the time constant circuit 11. Therefore, for example, when a plurality of ESD events occur successively in a short amount of time, an electric charge is further accumulated in a semiconductor integrated circuit apparatus due to reoccurrence of electrostatic discharge while a capacitor 11a of the time constant circuit 11 is charged. As a result, the N-channel transistor 14 is placed in an off state without sufficient discharge of the accumulated electric charge, which may result in destruction of an internal circuit.
Furthermore, while an N-channel transistor 11b having a negative threshold voltage is used in the time constant circuit 11, formation of such a special transistor complicates processes for manufacturing the semiconductor integrated circuit apparatus. This makes a cost increase unavoidable.